The manufacture of an integrated circuit in a microelectronics device involves the formation of several patterned metal layers that are successively overlaid upon one another to provide horizontal and vertical electrical pathways. These pathways are often referred to as metal wiring and are typically in the form of horizontal lines as well as vias and contacts which form vertical connections between the metal lines. An intermetal dielectric (IMD) layer is generally formed between the metal wiring to insulate the electrical pathways and prevent crosstalk that degrades device performance by slowing circuit speed.
With the constant demand for microelectronics devices that have a higher performance, the industry is in the mode of reducing the width and thickness of metal layers in device circuits. In addition, aluminum is being replaced by copper as the metal of choice in wiring schemes since the latter has a higher conductivity. Unfortunately, the fabrication of microelectronic devices with copper has some drawbacks. Copper does not etch as easily as Al and therefore copper layers are typically formed by a damascene process in which an opening is etched into an interlevel dielectric (ILD) layer and then a copper deposition is performed to fill the opening. Copper ions have a high tendency to migrate into an adjacent dielectric layer and therefore a barrier layer is usually formed between an ILD layer and a copper layer. Since oxides do not block copper ions and may easily react with copper to produce undesirable copper oxides that reduce the conductivity of the copper layer, a barrier layer is frequently comprised of nitrogen in the form of a metal nitride or silicon nitride.
During a damascene process, a second copper layer is often overlaid on a first copper layer in a substrate so that an electrical contact is possible between the two layers when a current is applied. However, in the sequence of steps to form an opening in the ILD layer that is aligned above the first copper layer, the first copper layer is exposed to etchants and chemicals that may corrode or react with copper. Therefore, a barrier layer which also functions as an etch stop layer is initially deposited on the first copper layer before the ILD layer is formed. A portion of the barrier layer remains in the device to block copper ions from diffusing into the overlying ILD layer. The portion of the barrier layer that functions as an etch stop is exposed to a fluorocarbon based plasma etch during formation of an opening in the ILD layer and is exposed to an O2 plasma during an ashing step to remove a photoresist pattern on the ILD layer. An important feature is that the etch stop prevents oxygen from attacking Cu to form a copper oxide. A subsequent etch step that may be based on a CH2F2 chemistry, for example, is used to remove the exposed portion of a silicon nitride barrier layer just prior to depositing the second copper layer.
A problem occurs during a popular method of depositing a silicon nitride barrier layer on the first copper layer by a plasma enhanced chemical vapor deposition (PECVD) process. The PECVD process usually involves SiH4, N2, and NH3 as reactant gases and the application of a RF power to form a plasma in which chemical bonds are broken in the reactant gases and reactive species recombine to form a stable silicon nitride layer on a substrate. During the PECVD process, SiH4 is easily converted to a reactive Si+4 species which readily reacts with an exposed copper layer in the substrate to form a copper silicide (CuSiX) layer on the copper. The thin CuSiX layer on the first copper layer is responsible for causing a metal leakage problem in the resulting device.
Another concern with a silicon nitride barrier layer is that silicon nitride has a poor adhesion to copper. Inadequate adhesion may lead to peeling of the silicon nitride barrier layer which has an adverse effect on the device performance and reliability. Therefore, a method is needed for retaining the good barrier properties of a silicon nitride layer while eliminating the copper adhesion issue and removing the concern about copper silicide formation.
An additional requirement of a barrier layer is that it should function as a dielectric layer to help insulate one metal layer from another. As such, the dielectric constant (k value) should be as low as possible. Most nitrogen containing barrier layers such as silicon nitride (k=7) or silicon oxynitride do not have a k value as low as a conventional silicon oxide (k=4) ILD layer.
A low leakage current SiCN barrier layer is described in U.S. Pat. No. 6,593,653. Although the k value can be reduced to about 4.9 in nitrogen doped silicon carbide (SiCN), this material is not as good a barrier as silicon nitride and may still result in copper silicide formation.
A SiC layer has been used as a barrier layer in a damascene process in U.S. Pat. No. 6,465,366. However, SiC is not as effective as silicon nitride in preventing copper diffusion in a copper damascene structure.
A succession of carbon doped SiO2 layers with increasing carbon content are formed between a substrate and an insulating layer in U.S. Pat. No. 6,570,256. While the intermediate layers improve adhesion of the insulating layer, they are not expected to function as good copper diffusion barrier layers in a copper damascene structure.
A dual damascene scheme that includes a silicon nitride hard mask formed on an oxide layer over a silicon substrate is disclosed in U.S. Pat. No. 6,602,806. However, forming an oxide layer on a substrate that contains an exposed conducting layer such as copper is generally not desirable since copper oxide will be formed which increases the resistivity of the device.
A composite etch stop layer consisting of a very thin silicon nitride layer and a thicker silicon oxynitride layer is described in U.S. Pat. No. 6,597,081. This composite layer is primarily designed to enable a better end point detection when stopping on the etch stop layer during the plasma etch to form an opening in an ILD layer in a damascene process.
Another composite etch stop layer is formed in U.S. Pat. No. 6,455,417 and includes a carbon doped SiO2 layer on a carbon doped silicon nitride layer. Both layers have a thickness from 10 to 1000 Angstroms and are deposited by a PECVD process in a damascene method.
A dual damascene method described in U.S. Pat. No. 6,479,391 involves a dual hard mask formed on an organic dielectric layer. A via and trench are formed in the hard mask layers and then the pattern is etch transferred into the underlying dielectric layer. The concern about forming a non-reactive barrier layer on a copper surface is not addressed.